Connector Pin Allocations

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Revision as of 21:49, 24 October 2016 by Andrewsm (talk | contribs) (Connector B Pinouts)
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Connector A Pinouts

Connector A
Pins Description
1 D0 (2)
2 D1 (3)
3 D2 (4)
4 D3 (5)
5 D4 (6)
6 D5 (7)
7 D6 (8)
8 D7 (9)
9 A0 (22)
10 A1 (23)
11 A2 (24)
12 A3 (25)
13 A4 (26)
14 A5 (27)
15 A6 (28)
16 A7 (29)
17 A8 (30)
18 A9 (31)
19 A10 (32)
20 A11 (33)
21 A12 (34)
22 A13 (35)
23 A14 (36)
24 A15 (37)
25 GND
  • Note 1: All DATA bus pins can be Tristate whilst ADDRESS pins will usually be Output only unless running A.D.T when they will be INPUT.
  • Note 2: Number in brackets refers to Arduino pin only.


Connector B Pinouts

Connector B
Pins Description
1 HOLD/S0 (40)
2 EMULATOR ENABLE (41)
3 INT/IRQ (42)
4 INTE/MREQ/NMI (43)
5 DBIN/RD/R/W (44)
6 WR (45)
7 SYNC (46)
8 HLDA/IORQ (47)
9 READY/RDY (48)
10 WAIT (49)
11 ADT O/E (50)
12 ADT ENABLE (51)
13 BUFFER CTLR (52)
14 AUDIO IN (Direct to Amp input via cap)
15 ANALYSER AQUIRE/EMULATOR STEP (A0)
16 ANALYSER RD/EMULATOR RUN (A1)
17 RELAY N/O
18 RELAY N/C
19 RELAY COM
20 N/A {MK1} / REFSH {MK2}
21 VCC (~8V DC, 100MA)
22 N/A {MK1} / M1 {MK2}
23 PSU +5V
24 N/A {MK1} / CLK {MK2}
25 GND
  • Note 1: All DATA bus pins can be Tristate whilst ADDRESS pins will usually be Output only unless running A.D.T when they will be INPUT.
  • Note 2: Number in brackets refers to Arduino pin only.
  • Note 3: Pin 20 on Mark 1 Systems is NC and on Mark 2 Systems it is REFSH
  • Note 4: Pin 22 on Mark 1 Systems is NC and on Mark 2 Systems it is M1
  • Note 5: Pin 24 on Mark 1 Systems is NC and on Mark 2 Systems it is CLK

8080 Pod Pinout Diagram

8080
POD DIP 40 DSUB Tester
Connector A
10 1 D0 (2)
9 2 D1 (3)
8 3 D2 (4)
7 4 D3 (5)
3 5 D4 (6)
4 6 D5 (7)
5 7 D6 (8)
6 8 D7 (9)
25 9 A0 (22)
26 10 A1 (23)
27 11 A2 (24)
29 12 A3 (25)
30 13 A4 (26)
31 14 A5 (27)
32 15 A6 (28)
33 16 A7 (29)
34 17 A8 (30)
35 18 A9 (31)
1 19 A10 (32)
40 20 A11 (33)
37 21 A12 (34)
38 22 A13 (35)
39 23 A14 (36)
36 24 A15 (37)
2 25 GND
Connector B
13 1 HOLD/S0 (40)
12 2 RESET/RES (41)
14 3 INT/IRQ (42)
16 4 INTE/MREQ/NMI (43)
17 5 DBIN/RD/R/W (44)
18 6 WR (45)
19 7 SYNC (46)
21 8 HLDA/IORQ (47)
23 9 READY/RDY (48)
NC 10 WAIT (49)
NC 11 SPARE (50)
NC 12 SPARE (51)
NC 13 BUFFER CRTL (52)
NC 14 AUDIO IN
NC 15 ANALOGUE A0
NC 16 ANALOGUE A1
NC 17 RELAY N/O
NC 18 RELAY N/C
NC 19 RELAY COM
NC 20 N/A {MK1} / REFSH {MK2}
NC 21 PSU VCC (~8V DC, 100MA)
NC 22 N/A {MK1} / M1 {MK2}
NC 23 PSU +5V
NC 24 N/A {MK1} / CLK {MK2}
2 25 GND

Z80 Pod Pinout Diagram

Z80
POD DIP 40 DSUB Tester
See Note*
Connector A
14 1 D0 (2)
15 2 D1 (3)
12 3 D2 (4)
8 4 D3 (5)
7 5 D4 (6)
9 6 D5 (7)
10 7 D6 (8)
13 8 D7 (9)
30 9 A0 (22)
31 10 A1 (23)
32 11 A2 (24)
33 12 A3 (25)
34 13 A4 (26)
35 14 A5 (27)
36 15 A6 (28)
37 16 A7 (29)
38 17 A8 (30)
39 18 A9 (31)
40 19 A10 (32)
1 20 A11 (33)
2 21 A12 (34)
3 22 A13 (35)
4 23 A14 (36)
5 24 A15 (37)
29 25 GND
Connector B
NC 1 HOLD/S0 (40)
NC 2 RESET/RES (41)
NC 3 INT/IRQ (42)
19 4 INTE/MREQ/NMI (43)
21 5 DBIN/RD/R/W (44)
22 6 WR (45)
NC 7 SYNC (46)
20 8 HLDA/IORQ (47)
NC 9 READY/RDY (48)
24 10 WAIT (49)
NC 11 SPARE (50)
NC 12 SPARE (51)
= 13 BUFFER CTLR (52)
NC 14 AUDIO IN
NC 15 ANALOGUE A0
NC 16 ANALOGUE A1
NC 17 RELAY N/O
NC 18 RELAY N/C
NC 19 RELAY COM
28 20 N/A {MK1} / REFSH {MK2}
NC 21 PSU VCC (~8V DC, 100MA)
27 22 N/A {MK1} / M1 {MK2}
NC 23 PSU +5V
6 24 N/A {MK1} CLK {MK2}
29 25 GND
  • Note 1: Z80 ONLY: Pull pins 27(M1) & 28(REFSH) high using two 10K Resistors, on Mark1 Testers
  • Note 2: Pin 20 on Mark 1 Systems is NC and on Mark 2 Systems it is REFSH
  • Note 3: Pin 22 on Mark 1 Systems is NC and on Mark 2 Systems it is M1
  • Note 4: Pin 24 on Mark 1 Systems is NC and on Mark 2 Systems it is CLK

6502 Pod Pinout Diagram

6502
POD DIP 40 DSUB Tester
Connector A
33 1 D0 (2)
32 2 D1 (3)
31 3 D2 (4)
30 4 D3 (5)
29 5 D4 (6)
28 6 D5 (7)
27 7 D6 (8)
26 8 D7 (9)
9 9 A0 (22)
10 10 A1 (23)
11 11 A2 (24)
12 12 A3 (25)
13 13 A4 (26)
14 14 A5 (27)
15 15 A6 (28)
16 16 A7 (29)
17 17 A8 (30)
18 18 A9 (31)
19 19 A10 (32)
20 20 A11 (33)
22 21 A12 (34)
23 22 A13 (35)
24 23 A14 (36)
25 24 A15 (37)
21 25 GND
Connector B
38 1 HOLD/S0 (40)
40 2 RESET/RES (41)
4 3 INT/IRQ (42)
6 4 INTE/MREQ/NMI (43)
36 5 DBIN/RD/R/W (44)
NC 6 WR (45)
7 7 SYNC (46)
NC 8 HLDA/IORQ (47)
2 9 READY/RDY (48)
NC 10 WAIT (49)
NC 11 SPARE (50)
NC 12 SPARE (51)
NC 13 BUFFER CRTL (52)
NC 14 AUDIO IN
NC 15 ANALOGUE A0
NC 16 ANALOGUE A1
NC 17 RELAY N/O
NC 18 RELAY N/C
NC 19 RELAY COM
NC 20 N/A {MK1} / REFSH {MK2}
NC 21 PSU VCC (~8V DC, 100MA)
NC 22 N/A {MK1} / M1 {MK2}
NC 23 PSU +5V
NC 24 N/A {MK1} / CLK {MK2}
21 25 GND

Mark1 VRAM Write Pod Amendment

The CPU pods will work just fine on their own, pin for pin as explained above. but if you require VRAM write access then a small Circuit is required.

The Circuit will need to be attached between the DATA lines of the Tester and the CPU Socket on the Test board. along with a few other lines depending on the CPU used

Schematics are bellow showing the Circuit and where to attach

  • Capacitor on the CLK and WAIT pin is a 390pF ceramic cap, tied to GND.
  • WAIT needs to be connected to Z80, Tester and Circuit
  • Other 4 capacitors are decoupling caps of 0.1uF.
  • +5v is coming from CPU SOCKET pin. (game board Power) Not from the tester.
  • CPU Pin M1 and REFSH will need 10K Ohm Pullups


Z80

VRAM Write Circuit

Note This circuit is only needed for Mark1 Testers, Made and Shipped in 2016 All Mark 2 Testers will incorporate this circuit within the Tester